Getting Started with RISC-V Beijing

The emergence of the RISC-V architecture has given rise to a demand for widely differing microarchitectural implementations, ranging from deeply embedded microcontrollers to DSPs to superscalar processors.

To meet the challenge of addressing so many different operating points it is necessary to abstract the architectural details and to automate the generation and verification of RISC-V processors.

The Codasip approach to delivering RISC-V processor IP is to employ the silicon-proven methodology of the high-level CodAL architecture description language and its suite of tools called Codasip Studio™ to implement various RISC-V microarchitectures

Using Codasip Studio (an Eclipse-based integrated processor development environment) designers write a high-level description (in CodAL architecture description language) of a processor and then automatically synthesize the design’s RTL, testbench, virtual platform models and processor SDK (C/C++ compiler, debugger, profiler, etc.). Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

Codasip has made various enhancements in order to optimize Codasip Studio and the CodAL language for the generation of RISC-V processors. The recently launched the 7th generation of Codasip Studio adds significant new functionality and features, making it the most advanced and effective technology on the market for tailoring RISC-V processors to meet chip designers’ application-specific needs.

Typical use cases for Codasip Studio are processor prototyping for a specific application domain, fast design space exploration, or development of custom extensions using Codasip’s architecture description CodAL language. In the last use case Codasip Studio generates hardware and corresponding SDKs that are aware of the custom extensions, including
• Readable Verilog or VHDL RTL and System Verilog UVM environments,
• testbenches and synthesis scripts,
• SDK consisting of LLVM based compiler, advanced profiling and debugging tools,
• both cycle-accurate and fast instruction-accurate simulation tools.

Codasip engineers have used the Codasip Studio design flow to create the broadest portfolio of RISC-V processors in the industry, and they now put the power in the hands of customers to further customize and extend the RISC-V instruction set, based on the unique requirements of the algorithms being run.

The presentation, among the other things, will cover the following new functionality:

• Improvements to SIMD support for up to 1024 bit.
• Native support for industry-standard AMBA interfaces, allowing for easy replacement of other processor cores while reusing your existing, proven peripheral IP.
• IEEE 1149-7-compatible 2-wire JTAG to minimize pin-count.
•        Major updates to software tools, including support for LLVM 6